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Counter 1 MHz input mod.

introduction permalink: http://www.amateurtele.com/index.php?artikel=221&id=#970
Since a couple of years I'm the proud owner of a Sayrosa model 261 frequency counter. It's a great device. The brand is quite unknown and I haven't seen any other device from Sayrosa. The counter can count until 600 MHz which's quite nice. There's an internal "OCXO". Well, it's a crystal with a heating element attached to it, but since I have a GPSDO time standard I want to use the generated stable 10 MHz signal for reference. Luckily there's an external female BNC clock signal input. Unfortunately the desired frequency is 1 MHz instead of 10 MHz. I'm designing a distribution device for the 10 MHz signal. The distributor should get eight selectable outputs. The selection is 10, 5 and 1 MHz and is should be possible to select a sinewave of square wave signal. But I guess the designing and building will take quite some time due to other priorities. Therefore I want to modify the frequency counter so it can handle the more standardised 10 MHz clock signal.

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initial design permalink: http://www.amateurtele.com/index.php?artikel=221&id=#971
I made a sketch of the desired circuit. The "heart" of the circuit is a 74LS390 chip (or related model like HC or HCT instead of LS) which is great for this purpose since it can divide by five and two! Therefore the 10 MHz signal can be divided by both and the result is the desired 1 MHz signal. Remind that the "divide by five" signal is a pulse signal and not a square wave. Dividing the 2 MHz signal by two "corrects" the signal to a nice (and desired) square wave. To terminate the 50 Ohms coax cable I've drawn a 47 Ohms resistor. (One 50 Ohms resistor or two 100 Ohms resistors in parallel would even be better. Normally a logic chip has a switching threshold of half the supply voltage. For example the switching threshold of a 5 VDC powered chip is normally 2,5 VDC. Therefore I've drawn two rather large (10 K) resistors to bias the input signal to 2,5 VDC. To decouple the 10 MHz RF signal is added one 470 pF capacitor. Since the logic signal is a square wave (sinewave with infinite harmonics) and I want a "perfect" sinewave I added a five pole 1 MHz low pass filter to suppress harmonics. The harmonics should be supressed at least 48,2 dBc. At first I wanted to be able to switch between the original 1 MHz signal and 10 MHz signal. But I can't imagine that I want to feed the counter with a 10 MHz signal and therefore the switch is discarded.

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real world circuit permalink: http://www.amateurtele.com/index.php?artikel=221&id=#972
The oscillator signal is directly fed into a divider chip and therefore the low pas filter and decoupling capacitor can be discarded form the design. Also the two resistors are replaced by a variable resistor. Apparently this chip has a threshold voltage of approximately 1,3 VDC. It turned out that two fixed resistors was too much of a hassle to get it right so I used a 10 kOhms variable resistor. For the middle region of the resistor the bias an be set quite nice. (Near 5 VDC and ground is the signal strength weakened.) The input’s of the not used dividers (the chip has more dividers on board than shown on the schematic) are connected to ground to prevent unwanted oscillations. The ground pins if the chip is soldered directly to the reference plane (ground plane) of the printed circuit board. The other components are soldered like the "dead bug" method to the chip. After setting the bias voltage, the circuit works great! There's an original switch on the back of the radio so the internal or external clock source can be selected. Therefore the counter can be used without an external clock signal.


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